1. Field of the Invention
The present invention relates to an integrated circuit, and more particularly to an integrated circuit in which an internal circuit is operated by a timing signal obtained by delaying a clock signal by a prescribed time as well as the clock signal.
2. Description of the Related Art
Generally, a dynamic circuit has been employed at times in a circuit part which is operated at high speed like a memory circuit, in the integrated circuit. The dynamic circuit serves to precharge an output with electricity during a certain period of a clock (For instance, when the clock has a voltage of low level) and output a logic during a remaining period of a clock (For instance, when the clock has a voltage of high level). However, when an input signal comes later than a logic decision period, the operation of the dynamic circuit may be possibly uncertain.
Thus, in order to overcome this problem, an attempt has been made that the logic decision period is shortened by a timing signal formed by delaying a clock signal and the input signal is determined before the logic decision period. FIG. 7 shows a diagram for explaining the constitution of a conventional circuit. Referring to FIG. 7, an integrated circuit 1 comprises a phase locked loop (PLL) circuit 2 for receiving an external clock signal 100 and an internal circuit 6. The internal circuit 6 is actuated by employing a signal 105 outputted from the PLL circuit 2 as a clock signal. A part of the circuit 6 is actuated by using a timing signal 106a formed by delaying the clock signal 105 by a delay device 7a. An external reset signal 101, an external input signal 102, an external output signal 103 and an external input and output signal 104 are inputted and/or outputted to the internal circuit 6 to carry out a desired processing.
FIG. 8 is a circuit diagram showing the internal construction of the delay device 7a. The delay device 7a comprises inverter circuits 10 which are connected in series in a plurality of stages. If the inverter has a delay of Tdinv per stage, the total of delay time of 2nxc3x97Tdinv may be obtained for the 2n stages.
FIG. 9 illustrates an example of a dynamic circuit which utilizes a delay signal. In this case, the dynamic circuit is constituted of a PMOS transistor 16 for precharging an output signal 113 with electricity, an NMOS transistor 17 for deciding a logic and an NMOS transistor 18 for determining the logic decision period. The output signal 111 of a logic circuit 19 is inputted to the NMOS transistor 17. The logical product signal of the internal clock signal 105 and a timing signal 106b delayed by a delay device 7b is formed by an AND circuit 20 to generate a logic decision period timing signal 112. The delay of the delay device 7b at this time is set to a value not smaller than that of the logic circuit 19.
FIG. 10 is a timing chart showing the operation of the dynamic circuit illustrated in FIG. 9. The signals the same as those of FIG. 9 are represented by the same symbols in FIG. 9.
FIG. 10A is a diagram showing timing under a standard condition upon design of a timing signal from a clock signal. As apparent from FIG. 10A, the clock signal 105 is delayed by the delay device 7b so that the timing signal 106b is formed. It is assumed that this delay time is Td. The logic decision timing signal 112 can be obtained from the logical AND of the internal clock signal 105 and the timing signal 106b. 
The output signal 111 of the logic circuit 19 which serves as the input signal of the dynamic circuit reaches the internal clock signal 105 with the delay of time Td logic. The dynamic circuit receives this signal and outputs a processing result when the logic decision timing signal 112 has high voltage. However, the output delay time of the logic circuit 19 increases because of unevenness or the like in a transistor performance, an incidental resistance component or an incidental capacity component at the time of forming the integrated circuit, so that it may become time Td logicxe2x80x2 which is larger than the time Td. Timing in this instance is illustrated in FIG. 10B.
The output signal of the dynamic circuit 113 forms temporarily a logic with the logic output signal 111 which is not changed, and then the output signal 113 is changed again by the logic output signal 111 which has been changed. The output signal of the dynamic circuit 113 only changes from the voltage of high level to the voltage of low level. Therefore, if the output signal of the dynamic circuit 113 is located at the voltage of low level when it should be located at the voltage of high level, the output is disadvantageously kept located at the voltage of low level, which inconveniently causes the dynamic circuit to be operated in a wrong way.
As shown in FIG. 10C, even if the cycle of the internal clock signal 105 is lengthened, the dynamic circuit cannot be returned to a normal operation because the delay time Td is not changed. In order to avoid such phenomenon, it is necessary to provide a margin between the time Td and the time Td logic and design the dynamic circuit so as to be operated normally even when there is unevenness in the margin. If the cycle of the internal clock signal 105 is short, the time corresponding to this margin between the time Td and the time Td logic becomes so large as not to be neglected relative to the cycle of the clock. Consequently, the performance of the dynamic circuit is undesirably deteriorated. Thus, the margin between the time Td and the time Td logic needs to be deleted as much as possible.
A voltage controlled oscillator 5 forming the PLL 2 constitutes a loop by connecting inverters in series in a plurality of stages. The voltage controlled oscillator 5 is equipped with a mechanism for controlling the delay time by these inverters so that it serves to control oscillating frequency. An output signal is outputted from a terminal at an intermediate part of the connection of the inverters so that a timing signal can be formed. However, this timing signal thus formed needs to be distributed to the internal circuit 6 similarly to the internal clock signal 105. In this case, the time of the internal clock signal 105 which arrives at the internal circuit 6 needs to coincide with the time of the timing signal which arrives at the internal circuit 6. It has been disadvantageously difficult to realize the coincidence of the arrival time of these signals.
The present invention has been devised in order to overcome the above-mentioned shortcomings of the prior art and it is an object of the present invention to provide an integrated circuit capable of designing operating frequency as high as possible by deleting a margin in delay time even when a timing signal is formed from a clock signal by a delay device.
In order to achieve this object, an integrated circuit according to the present invention comprises: a phase locked loop circuit which feeds back the oscillating output signal of a voltage controlled oscillator and controls the oscillating frequency of the oscillator based on the result of comparison of the phase between an oscillating output signal and an externally supplied clock signal, and a delay device which delays the oscillating output signal by a prescribed time, the integrated circuit being operated by using the signal thus delayed, and the delay device controlling the change of the delay time depending on a control signal corresponding to the above-mentioned phase comparison result.
As described, according to the integrated circuit of the present invention, a margin is not given to the timing signal and a delay time generated by the internal delay device is designed to be externally controlled. Accordingly, since the delay of the delay device for forming the timing signal of the internal circuit is also changed, the internal circuit can be operated in a normal manner even if the operating frequency is changed to lower than usual. Therefore, even when a margin is deleted upon design of the operating frequency, the internal circuit can be operated in a normal way by adjusting the clock frequency.